An arrangement of this type is known from the document EP-A-449,659.
For a linear operation of the charge pump circuit it is necessary that the two current sources, which respectively charge and discharge the storage capacitance, can be active at the same time. In this way even the smallest shift in time between the up and the down command applied to the current sources of the charge pump will result in a net charge of the storage capacitance and in this way a "dead zone" in the control of the voltage across this capacitance is avoided.
However, the time during which the two current sources of the charge pump are simultaneously active should be minimised, on the one hand for reasons of current consumption, which is of particular importance when the application is of the battery-powered portable type, and on the other hand for noise reasons, bearing in mind that the noise across the storage capacitance may be considered to be zero when the two current sources are inactive and that noise appears when the two current sources are active, which noise originates both from said current sources and from their command signal.
Thus, the technical problem to be solved is to minimised the time interval during which the two current sources of the charge pump are simultaneously active.
From a technological perspective it appears that the response times are longest in the part relating to the charge pump, which employs transistors of large dimensions, whereas the control signals can be obtained by means of low-consumption logic circuits whose switching times are substantially smaller.
Therefore, it has been proposed to use the up and down commands in order to detect in a logical manner the instant at which these commands are simultaneously active and to apply the resulting signal to a delay device which allows for the comparatively large rise time of the current in the current sources of the charge pump. The signal from this delay device is then applied to a reset input of the phase detector or, which amounts to the same, to a logic device which sets the up and down command signals to their inactive logic levels.
A conventional delay device comprises a plurality of logic gates arranged in series, the delay obtained at the output of this device being equal to the sum of response times of all the gates of the device. If the performance of such a system as a function of temperature is now considered it appears that the delay produced by the delay device can be adapted correctly to the rise times of the current sources of the charge pump at a given temperature, whilst at the limit temperatures of the specified temperature range this delay is completely maladjusted.
Differences in performance as a function of the temperature arise in particular from the fact that different technologies are used for the gates forming the delay device and for the current sources of the charge pump.
In order to mitigate this problem it has also been proposed to use one of the transistors of each of the current sources of the charge pump for generating two signals which, combined by a logic gate, provide the reset signal at the output. In accordance with this technique the current supplied in the course of time is measured within the charge pump itself, so that this measurement allows for the temperature characteristics of said current sources.
Such a technique is therefore more accurate than the preceding one but has a disadvantage when such a circuit is to be operated at a low supply voltage. Two transistors in one of the current sources of the charge pump then have to be reserved exclusively for producing the signal for resetting the up and down commands, without the current supplied by these two transistors being used for charging and discharging the storage capacitance.
This is caused by the fact that if the current of the relevant transistors would be used for charging or discharging the storage capacitance this would result in the voltage swing available across this storage capacitance being reduced by two forward diode voltages.
Therefore, if low voltage operation is required with a maximal swing at the output of the phase-locked circuit, this means that two transistors, whose areas are not negligible, have to be reserved for measuring the current, the current supplied by them not being used for charging and discharging the storage capacitance.